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Parallax Propeller
The Parallax P8X32A Propeller chip, introduced in 2006, is a multi-core architecture parallel microcontroller with eight 32-bit RISC CPU cores.〔(makezine.com )〕〔(makezine.com )〕
The Parallax Propeller microcontroller, Propeller Assembly language, and Spin interpreter were designed by one person, Parallax's co-founder and president Chip Gracey. The Spin programming language and "Propeller Tool" integrated development environment were designed by Chip Gracey and Parallax's software engineer Jeff Martin.
On August 6, 2014, Parallax Inc. released the Propeller P8X32A Verilog and top-level HDL files under the GNU General Public License 3.0.〔(Propeller 1 Open Source page )〕
==Multi-core architecture==
Each of the eight 32-bit cores (called a cog) has a CPU which has access to 512 32-bit long words (2 KB) of instructions and data. Self-modifying code is possible and is used internally, for example as the boot loader overwrites itself with the SPIN Interpreter. Subroutines in SPIN (object-based high-level code) utilize a call/return mechanism requiring the use of a call stack. Assembly (PASM, low-level) code does not require a call stack. Access to shared memory (32 KB RAM; 32 KB ROM) is controlled in round-robin fashion by an internal bus controller called the hub. Each cog also has access to two dedicated hardware counters and a special "video generator" for use in generating PAL, NTSC, VGA, servo-control, or other timing signals.〔(electronicdesign.com )〕
抄文引用元・出典: フリー百科事典『 ウィキペディア（Wikipedia）』
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